Conventionally, as the method for establishing communications between cores (or function blocks), each which operates at a different clock frequency, there are chiefly two types of communication method, that is, synchronous system and asynchronous system.
FIG. 12 is a diagram illustrating a semiconductor device for establishing communications in the synchronous scheme.
When communications between cores A and B are established by such a semiconductor device, the synchronous scheme requires that the clock frequency ratio for two cores in communication is 1:times of integer number (for example, 1:2, 1:3, . . . , etc.) or 1:a fraction of integer number (for example, 1:½, 1:⅓, . . . , etc.) and that the phases of two clocks must be equalized. That is, the synchronous communication can be established between only the cores in which clocks are in synchronous state.
FIG. 13 is a diagram illustrating a semiconductor device for establishing communications in the asynchronous scheme.
Communications between cores, in which the clock frequency ratio of two cores is not 1:times of integer number or 1:times of a fraction of integer number and the phase between two clocks is not equalized, are called asynchronous communications. In the asynchronous communications, the timing with which signals are output and the timing with which signals are input are in asynchronous relationship. The signal fluctuates between “0” and “1” for a certain time period (called “metastability”). For that reason, a technique of using a synchronizing circuit to prevent an erroneous operation due to metastability is generally provided (refer to, for example, patent document 1).
According to the technique disclosed in the patent document 1, a synchronizing circuit is disposed between a first core that performs a predetermined operation in sync with the first clock signal and a second core that performs a predetermined operation in sync with the second clock signal. The synchronizing circuit latches the output data of the first core in sync with the first clock signal and thus outputs the latched signal in sync with the second clock signal.
Moreover, the technique of preventing an erroneous operation due to metastability is proposed (refer to, for example, patent document 2).
In the technique disclosed in the patent document 2, changes of the data input signal and the clock input signal are detected. When the setup time or hold time is satisfied, the erroneous operation caused by metastability is prevented by controlling in such a way that the data input signal of the flip-flop is not changed.
[Patent Document 1]
Japanese Patent laid-open publication No. 2003-273847
[Patent Document 2]
Japanese Patent laid-open publication No. H6-45880